Custom cores
SPI logic built to your interface, bus and toolchain.
What we build
Custom cores start from one of the standard cores or from a blank specification. They follow the same rules: synthesizable, single clock domain unless your design needs otherwise, and delivered with self-checking testbenches.
| Typical request | Scope |
|---|---|
| Dual / Quad SPI | Two or four data lines for flash and fast peripherals |
| Multi-subordinate fabrics | Several subordinates or chip selects behind one main |
| CRC / frame counters | Integrity checks and sequence counting in the frame path |
| Bus wrappers | AXI4-Stream, Avalon, Wishbone |
| HDL versions | Verilog or SystemVerilog |
| Vendor packaging | Packaged for a vendor tool flow, e.g. Vivado IP catalog or LabVIEW FPGA IP Integration Node |
How an engagement runs
- 1RequirementsYou send the interface, clock frequency, target device, toolchain and any timing limits.
- 2SpecificationWe return a written specification: ports, timing, limits and test plan. You approve it before RTL work starts.
- 3RTL + testbenchSynthesizable HDL and a self-checking testbench that checks the core against the specification.
- 4DeliverySource or netlist, datasheet and integration notes, as agreed.
Typical lead time: [to fill in]. Pricing model: [to fill in].
What to include in a request
- Target FPGA family or part number, toolchain and version
- System clock frequency and required SCLK
- SPI modes, word width, number of subordinates
- Host-side interface: plain ports or a named bus
- HDL language and deliverable: source or netlist
Start a custom core
Use the quote form and choose “Custom development”, or write to sales@spilib.com.