IP Cores
Four SPI cores in synthesizable VHDL, for any FPGA family.
Comparison
| Core | Role | SPI modes | Word / frame | SCLK | Input handling | Host side |
|---|---|---|---|---|---|---|
| SPI Main | Main | 0–3; CPOL/CPHA at runtime | 8, 16 or 32 bits (generic), MSB first; multi-word frames under one CS | fclk/(2·(div+1)), 16-bit div write ≤ fclk/2 read-back ≤ fclk/6 | MISO double-registered | — |
| SPI Main Frame | Main | 0–3; CPOL/CPHA at runtime | One trigger sends N words under a single CS | as SPI Main | as SPI Main | Valid/request stream handshake; frame-wide busy and done |
| SPI Sub | Subordinate | 0–3 | Continuous multi-byte frames under one CS; next-word staging at word boundaries | ≤ fclk/10 | Asynchronous SCLK, CS, MOSI synchronised to fclk | MISO output-enable for shared buses |
| SPI Tunnel | Main over a tunnel link, e.g. a SerDes SPI bridge | 0 (fixed by the link) | 1–15-byte commands | — | Bridge handshake; stale-buffer drain | Subordinate-select commands; timeout with safe release; debug state output |
Common to all cores
| HDL | Synthesizable VHDL |
|---|---|
| Clock domains | 1 |
| Reset | Synchronous, active-high |
| Port types | std_logic only |
| Vendor primitives | None |
| Verification | Self-checking testbenches, shipped with the core |
Resource utilisation
LUT, FF and Fmax figures are published per device after synthesis. Until then, ask sales for your target.
Not sure which core?
Use SPI Main for single words or short transfers, SPI Main Frame when a FIFO feeds whole frames, SPI Sub when the FPGA is the subordinate. For anything else, see custom cores.
Evaluation netlists are built for one named device and toolchain. Licensing & evaluation