The SPI Main core drives an SPI bus from FPGA logic. SPI mode (CPOL, CPHA) and the SCLK divider are set at runtime, so one build serves devices with different bus settings. Word width is a generic: 8, 16 or 32 bits. Several words can be sent under one chip select. The MISO input is double-registered before use.
Features
All four SPI modes; CPOL and CPHA set at runtime
16-bit clock divider: SCLK = fclk / (2·(div+1))
MSB first
Word width 8, 16 or 32 bits, selected by generic
Multi-word frames under one chip select
Double-registered MISO input
Single clock domain; synchronous active-high reset; std_logic-only ports; no vendor primitives
Self-checking testbenches included
Block diagram
Fig. 1 SPI Main core, functional view. clk and rst reach every block and are not drawn. W = word width generic.
Specifications
Parameter
Value
HDL
VHDL, synthesizable
Clock domains
1 (fclk)
Reset
Synchronous, active-high
SPI modes
0, 1, 2, 3; CPOL/CPHA at runtime
Bit order
MSB first
Word width
8, 16 or 32 bits (generic)
SCLK divider
16-bit; SCLK = fclk / (2·(div+1))
Frames
Multi-word under one chip select
MISO input
Double-registered
Port types
std_logic only
Vendor primitives
None
Verification
Self-checking testbenches
Interface
Port
Dir
Width
Description
clk
in
1
System clock, fclk
rst
in
1
Synchronous reset, active-high
cpol
in
1
Clock polarity
cpha
in
1
Clock phase
clk_div
in
16
SCLK divider value
start
in
1
Start a transfer
tx_data
in
W
Word to send
rx_data
out
W
Word received
busy
out
1
Transfer in progress
sclk
out
1
SPI clock
cs_n
out
1
Chip select, active low
mosi
out
1
Main out, subordinate in
miso
in
1
Main in, subordinate out
Port list for orientation; the datasheet is authoritative. W = word width generic.
Performance
Transfer
SCLK ratio
@ fclk = 40 MHz
@ fclk = 100 MHz
Write
fclk/2
20 MHz
50 MHz
Read-back
fclk/6
6.67 MHz
16.7 MHz
Verified in simulation. Maximum SCLK on hardware also depends on board, I/O timing and the connected device.
Vendor-neutral VHDL with no vendor primitives or constraints. The source licence targets any family listed under supported FPGA vendors, including NI LabVIEW FPGA targets through the IP Integration Node. An evaluation netlist is built for one named device and toolchain version.