The SPI Sub core makes the FPGA an SPI subordinate. SCLK, CS and MOSI arrive asynchronously and are synchronised into the system clock, so the whole core runs in one clock domain. It handles continuous multi-byte frames under one chip select and stages the next word at word boundaries. A MISO output-enable supports shared buses.
Features
Asynchronous SCLK, CS and MOSI synchronised into the system clock
All four SPI modes
Continuous multi-byte frames under one CS
MISO output-enable for shared buses
Next-word staging at word boundaries
Single clock domain; synchronous active-high reset; std_logic-only ports; no vendor primitives
Self-checking testbenches included
Block diagram
Fig. 1 SPI Sub core, functional view. clk and rst not drawn.
Specifications
Parameter
Value
HDL
VHDL, synthesizable
Clock domains
1 (fclk)
Reset
Synchronous, active-high
SPI modes
0, 1, 2, 3
Input handling
SCLK, CS, MOSI synchronised to fclk
Frames
Continuous multi-byte under one chip select
Word staging
Next word staged at word boundaries
MISO
Output-enable for shared buses
SCLK limit
≤ fclk/10
Port types
std_logic only
Vendor primitives
None
Verification
Self-checking testbenches
Interface
Port
Dir
Width
Description
clk
in
1
System clock, fclk
rst
in
1
Synchronous reset, active-high
cpol
in
1
Clock polarity
cpha
in
1
Clock phase
rx_data
out
8
Byte received
rx_valid
out
1
Byte received strobe
tx_data
in
8
Next byte to send
sclk
in
1
SPI clock from main
cs_n
in
1
Chip select, active low
mosi
in
1
Main out, subordinate in
miso
out
1
Main in, subordinate out
miso_oe
out
1
MISO output enable
Port list for orientation; the datasheet is authoritative. W = word width generic.
Performance
Transfer
SCLK ratio
@ fclk = 40 MHz
@ fclk = 100 MHz
Sub
fclk/10
4 MHz
10 MHz
Verified in simulation. Maximum SCLK on hardware also depends on board, I/O timing and the connected device.
Vendor-neutral VHDL with no vendor primitives or constraints. The source licence targets any family listed under supported FPGA vendors, including NI LabVIEW FPGA targets through the IP Integration Node. An evaluation netlist is built for one named device and toolchain version.