SPI IP cores · synthesizable VHDL

SPI IP cores for FPGAs, in vendor-neutral VHDL.

Four standard cores: an SPI main, a main with a frame sequencer, an SPI subordinate and an SPI tunnel controller for SerDes links. Single clock domain, std_logic-only ports, self-checking testbenches. Custom cores are built to your interface and toolchain.

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Fig. 1 SPI mode 0 (CPOL = 0, CPHA = 0), one 8-bit word, MSB first. CS active low; data changes on the falling SCLK edge and is sampled on the rising edge.

Standard cores

Full comparison

SCLK limits are ratios to the system clock f_clk, verified in simulation. Resource figures are published per device after synthesis.
Core	Function	SPI modes	Word / frame	SCLK limit
SPI Main	Runtime-configurable SPI main	0–3, set at runtime	8, 16 or 32 bits; multi-word under one CS	write f_clk/2 read-back f_clk/6
SPI Main Frame	SPI Main plus frame sequencer: one trigger sends N words	0–3, set at runtime	N words under one CS; valid/request handshake	as SPI Main
SPI Sub	SPI subordinate; SCLK, CS, MOSI synchronised to f_clk	0–3	Continuous multi-byte frames under one CS	f_clk/10
SPI Tunnel	SPI tunnelled across a link, e.g. a SerDes; bridge protocol handled in logic	0 (fixed by the link)	1–15-byte commands	—

Custom cores

When a standard core does not fit, we build one to your specification: interface, bus wrapper, HDL and packaging. You approve a written specification before RTL work starts.

How a custom engagement runs

Dual / Quad SPI
Multi-subordinate fabrics
CRC and frame counters
AXI4-Stream, Avalon, Wishbone wrappers
Verilog or SystemVerilog versions
Vendor-specific packaging

Supported FPGA vendors

Vendor-neutral VHDL — no vendor primitives or constraints, so the cores move between toolchains unchanged.

Vendor	Families	Toolchain
AMD (Xilinx)	7 Series, UltraScale, UltraScale+, Versal	Vivado
Altera (Intel)	Cyclone, Arria, Stratix, Agilex	Quartus Prime
Lattice	ECP5, CertusPro-NX, Certus-NX, MachXO3/5	Radiant / Diamond
Microchip	PolarFire, SmartFusion2, IGLOO2	Libero SoC
Efinix	Trion, Titanium	Efinity
Gowin	GW1N, GW2A, Arora	Gowin EDA
NI	LabVIEW FPGA targets (FlexRIO, incl. PXIe-1487)	IP Integration Node

Request a quote, a source licence or an evaluation netlist.

Name the core, the target device and the toolchain. Or write to sales@spilib.com.

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